Some applications for semiconductor devices require metal-oxide semiconductor (MOS) transistors that can operate at relatively high voltages. A cross-section view of a high voltage MOS transistor (e.g., an NMOS transistor 100) is shown in FIG. 1. The NMOS transistor 100 can be fabricated in a P type substrate (P substrate) 102. In the P substrate 102, a heavily doped P+ implant region 104 (bulk), a heavily doped N+ source region 106 (source) and a lightly doped drain implant N well 108 (N− well) can be formed. In the N− well 108, a heavily doped N+ drain region 110 (drain) can be further formed. A gate oxide layer 112 is formed over the P substrate region between the source 106 and the drain 110. A gate 114 can be then formed over the gate oxide layer 112. Furthermore, to achieve a targeted threshold gate voltage, a doping concentration of the shallower P substrate region under the gate oxide layer 112 is higher than that of the P substrate region far away from the surface of the P substrate 102. Such heavily doped P substrate region under the gate oxide layer 112 is called an adjustment implant layer 116 (PA layer). The NMOS transistor 100 is realized in a layout structure composed by linear strips. As the lightly doped drain region (N− well 108) extends under the gate oxide layer 112, the N− well 108 intersects with the PA layer 116. As such, a linear planar PN junction 118 is formed between the N− well 108 and the PA layer 116.
As shown in FIG. 1, a distance from a location of the linear planar PN junction 118 to the center of the drain 110 is denoted as D. The linear planar PN junction 118 can be a curved junction rather than an ideal plane junction. As a result, a drain breakdown voltage of the NMOS transistor 100 is determined by an avalanche breakdown voltage of the linear planar PN junction 118. Therefore, due to a junction curvature effect of the curved junction, the avalanche breakdown voltage of linear planar PN junction 118 is decreased. Consequently, the drain breakdown voltage of the NMOS transistor 100 can be decreased.
As the drain breakdown voltage is regarded as one of the important design parameters of high voltage MOS transistors, various methods have been proposed so as to counterbalance the junction curvature effect. These methods include changing the thickness of the gate, changing the drain doping profile, and implementing multiple doping layers in the drain region. However, the above-mentioned methods may need supplementary processing steps and supplementary masks, which may increase costs of MOS transistors.